Space-Time Adaptive Processing on the Mesh Synchronous Processor

■ This article examines the suitability of the Mesh synchronous processor (MeshSP) architecture for a class of radar signal processing algorithms known as space-time adaptive processing (STAP), which is an important but computationally demanding technique for mitigating clutter and jamming as seen by an airborne radar. The high computational requirements of STAP algorithms, combined with the need for programming flexibility, have motivated Lincoln Laboratory to investigate the application of commercially available massively parallel processors to the STAP problem. These processors must be sufficiently flexible to accommodate different STAP architectures and algorithms, and must be scalable over a wide parameter space to support the requirements of different radar systems. The MeshSP offers high peak-signal-processing performance in a small form factor, which makes it attractive for airborne radar environments. An algorithm implementation must be reasonably efficient to take advantage of this performance. The implementation efficiency depends on four factors: the computational details of the algorithm, the chosen decomposition of the algorithm into constituent parts capable of parallel execution, the subsequent mapping of these parallel components onto the processor, and the underlying suitability of the architecture of massively parallel processors. This article describes performance models and methods of estimating MeshSP efficiency on representative STAP algorithms in order to assess the potential use of MeshSP in airborne STAP applications.